Conventional remote control units such as those for controlling digital televisions, set top boxes or video recorders, generate infrared (IR) or radio frequency (RF) signals comprising serial binary pulse trains where the signal coding is represented by variations in pulse width. When a given button on the remote control unit is pressed to instruct the device to perform a particular function, the remote control unit generates and transmits a serial binary pulse train signal. The variations in the width of the pulses in the signal are a form of code defining the particular instruction. Thus, a signal defining an instruction to increase volume would have different pulse width variations than a signal defining an instruction to change channels. In conventional decoders, control of the storage of values representing each pulse width and position in the pulse train is given to a main processor which has to stop normal processing operations to store the pulse values.
Referring to FIG. 1, a conventional decoder unit 10 such as that found in a digital set top box is shown. The decoder unit 10 includes a system processor or CPU 12, a random access memory (RAM) 14, an address decoder unit 16 and a level transition timer (LTT) 18. The CPU 12, RAM 14, address decoder 16 and LTT 18 all communicate through a system bus 20. The LTT 18 is additionally connected directly to the CPU 12 via an interrupt line 22. The LTT 18 is arranged to receive the pulse train signal transmitted by the remote control unit (not shown).
In practice the actual signal transmitted by the remote control unit consists of the pulse train signal modulated onto a carrier signal. The transmitted signal is initially received by a demodulator unit (not shown) which demodulates the signal in order to extract the pulse train. The pulse train is then applied to the LTT 18 in a form such as that shown generally at 100 having a series of pulses 102 whose width varies in a predetermined manner depending on the instruction that the signal is intended to represent.
In order to decode the pulse train signal transmitted by the remote control unit, the decoder unit 10 must determine the width of each pulse in the signal. This is normally achieved by monitoring the time of each change of state in the pulse train. Such changes of state occur at the start and end of each pulse where the level of the signal changes from 0 to 1 or 1 to 0 and are referred to as “level transitions” or “pulse edges”. Each pulse edge triggers the generation of a counter value in the LTT 18 indicating either the time elapsed from the last detected pulse edge or the absolute time of the pulse edge from the start of the pulse train signal depending on the system used. As the time of each pulse edge is captured by the LTT 18 and the counter value is generated, the LTT 18 applies an interrupt signal to the CPU 12 via the interrupt signal line 22. This causes the CPU 12 to suspend carrying out its current task (e.g., processing the received television signal) and begin an interrupt service routine (ISR). The ISR involves the CPU 12 performing a number of tasks as illustrated in the flow diagram of FIG. 2.
On receipt of the interrupt signal from the LTT 18 on line 22 (step a) the CPU 12 completes any current or pending instruction or task being performed (step b) and then suspends the carrying out of any further tasks and branches to the ISR (step c). The CPU 12 copies the contents of any registers containing system or program data used by the CPU 12 for its previous tasks to a portion of memory (e.g., RAM 14) in a process known as “stacking” (step d). The stacking provides register space for any data required by the CPU 12 for carrying out the ISR. The CPU 12 then interrogates the system hardware to determine the source of the interrupt signal (step e). When the CPU 12 determines the LTT 18 is the source of the interrupt signal, the CPU 12 reads the counter value for the last pulse edge (step f) and writes this value to a cyclic buffer 24 in the RAM 14 via the address decoder 16 and system bus 20 (step g). The CPU 12 checks whether the last pulse edge defines the start of a new instruction (step h) and if it does not, the CPU 12 then restores its register contents by reading the original system data from the stack 24 and writing the data back into the CPU registers (step i). When the register contents have been restored, the CPU returns from the ISR to process normal tasks until the next interrupt signal is received (step j).
This process is repeated for each pulse edge or level transition in the pulse train. Once all of the pulses in the pulse train have been received and the counter values for each pulse edge have been written to the cyclic buffer in the RAM 14, the CPU 12 reads the sequence of counter values from the cyclic buffer 24 for decoding. The sequence of counter values in the cyclic buffer 24 represents either the absolute times of the pulse edges or the time elapsed between each pulse edge and thus constitutes a code defining a specific instruction. The CPU 12 then either applies the code to a separate decoding unit which decodes the signal and returns the appropriate instruction or, more usually, decodes the instructions itself.
An interrupt signal is generated by the LTT 18 on every pulse edge of the pulse train signal. The CPU 12 is required to execute an ISR at each pulse edge. Since individual pulse trains often contain in excess of 10 pulses (20 level transitions) and occasionally up to and above 100 pulses (200 level transitions), significant system latency is associated with receiving and decoding such signals. Such a latency (measured in number of processor cycles) can be estimated as:    step d (stack register contents) 50 cycles;    step e (determine interrupt source) 25 cycles;    step f (read counter value) 5 cycles;    step i (restore register contents) 50 cycles.
Thus, the executing of each ISR delays the CPU 12 from continuing with its normal tasks for approximately 135 processor cycles, which is a considerable portion of the instantaneous processing power provided by the CPU 12. The reception and decoding of the pulse train could prevent the CPU 12 from adequately performing normal tasks.
It would be advantageous to provide a method and/or apparatus for receiving and decoding a demodulated pulse train which reduces the burden on the system processor within the decoder unit.